Silicon carbide vertical FET and method for manufacturing the sa

Details Silicon carbide vertical FET and method for manufacturing the sa Silicon carbide vertical FET and method for manufacturing the sa

1999-01-05

2000-09-12

Tran, Andrew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438273, 438285, 438589, H01L 21336, H01L 213205

Patent

active

061177350

ABSTRACT:
In a method for forming a silicon carbide vertical FET, a first mask and a second mask that overlaps the first mask are used so that a first conductivity type impurity region is defined by one end of a certain portion of the first mask, and that portion of the first mask and the second mask are then removed so that a second conductivity type impurity region is defined by another portion of the first mask. Thus, the first conductivity type impurity region and the second conductivity type impurity region are positioned relative to each other, with respect to the first mask. If a mask including a tapered end portion is used, and ion implantation is conducted with different accelerating-field voltages, the first conductivity type region and the second conductivity type region may be formed by self-alignment, using only one mask. By controlling the impurity concentration of the channel region, the threshold voltage can be controlled, and a normally-off type FET can be provided.

REFERENCES:
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patent: 5539217 (1996-07-01), Edmond et al.
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patent: 5895939 (1999-04-01), Ueno
patent: 5963807 (1999-10-01), Ueno
patent: 5969378 (1999-10-01), Singh
patent: 6054352 (2000-04-01), Ueno
SiC Integrated MOSFETS,by S.Onda,Kumar, and Hara,Research Laboratories, Nisshin,Aichi 470-01,Japan,pp. 369-388, Month Unknown 1997.

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