Semiconductor integrated circuit

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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36518909, G11C 1300

Patent

active

060210710

ABSTRACT:
In an output circuit of a memory IC having a programmable impedance buffer function, the output circuit includes n MOS transistors having drains connected to an external output node and having channel widths increasing in progression from 2.sup.0 times to 2.sup.(n-1) times the unit channel width, m output control signal lines connected to the gate nodes of m transistors which are part of the n MOS transistors, and state fixing lines connected to the gate electrodes of the remaining (n-m) transistors among the n MOS transistors, for fixedly setting the (n-m) transistors into the nonconductive state. With this construction, the impedance matching precision is enhanced and the cost is lowered.

REFERENCES:
patent: 5136542 (1992-08-01), Abe et al.
Harold Pilo et la.: IEEE International Solid-State Circuits Conference; Session 9 SRAM FA 9.3: A 300MHz, 3.3V 1Mb SRAM Fabricated in a 0.5.mu.m CMOS Process; 1996; pp. 1, 7 148-149.

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