Method to simultaneously fabricate the self-aligned silicided de

Details Method to simultaneously fabricate the self-aligned silicided de Method to simultaneously fabricate the self-aligned silicided de

1998-04-07

2000-02-01

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438281, 438592, H01L 218234, H01L 21336

Patent

active

060202408

ABSTRACT:
The present invention discloses a method to simultaneously fabricate the self-aligned silicided devices and ESD protective devices in a substrate. A functional region and a ESD protective region are defined on the substrate and each region has a gate structure. Firstly, lightly doped drain (LDD) regions are formed in both of the region by an ion implantation process. An N-type conducting dopants are implanted into the ESD protective region. Afterwards, the spacers of the gate structures are defined for isolation. A thermal oxidation process is done to grow a thin pad oxide on the functional region and a thicker pad oxide on the ESD protective region. A blanket implantation is performed on all NMOS device. After the implantation process, a RTP process is done to activate the dopants in the substrate and to recover implant damages. Finally, the thin pad oxide layer is removed by using a wet etching process and a self-aligned silicide layers are defined on the gate, source and drain regions of the functional region.

REFERENCES:
patent: 5374565 (1994-12-01), Hsue et al.
patent: 5585299 (1996-12-01), Hsu
patent: 5672527 (1997-09-01), Lee
patent: 5723352 (1998-03-01), Shih et al.
K. Fujii et al., A Thermally Stable Ti-W Salicide for Deep-Submicron Loic with Embedded DRAM, 1996 IEEE, pp. 451-454 no month.
Ajith Amerasekera et al., Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 .mu.m CMOS Process, 1996 IEEE, pp. 893-896 no month.
Shye Lin Wu et al., Characterization of Thin Textured Tunnel Oxide Prepared by Thermal Oxidation of Thin Polysilicon Film on Silicon, IEEE Transactions on Electron Devices, vol. 43, No. 2, Feb. 1996, pp. 287-294.

Affiliated with

Also associated with

Rating

Method to simultaneously fabricate the self-aligned silicided de does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to simultaneously fabricate the self-aligned silicided de, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to simultaneously fabricate the self-aligned silicided de will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-937147