Output precharge circuit for memory

Details Output precharge circuit for memory Output precharge circuit for memory

1993-07-23

1994-12-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36518905, 36518908, 326112, 327 51, G11C 700, H03K 190175

Patent

active

053771494

ABSTRACT:
The invention relates to memories made in integrated circuit form and, particularly, to high capacity memories that need to have fast access time. The invention provides for carrying out a reading in two stages: precharging and then reading. A precharging is done, at an intermediate value, between the high logic level and the low logic level, of the data output pads at which the information elements read in the memory appear. A circuit to memorize the logic state on the pad and a threshold inverter enable this result to be obtained.

REFERENCES:
patent: 4881203 (1989-11-01), Watanabe
patent: 4893276 (1990-01-01), Okuyama
patent: 4988888 (1991-01-01), Hirose
patent: 5058066 (1991-10-01), Yu
patent: 5151621 (1992-09-01), Goto
patent: 5204838 (1993-04-01), Son
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, New York, US, pp. 1060-1066, Kohno et al., "A 14-NS 1-Mbit CMOS SRAM with Variable Bit Organisation".

Affiliated with

Also associated with

Rating

Output precharge circuit for memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output precharge circuit for memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output precharge circuit for memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-923438