Semiconductor memory with selectively enabled precharge and sens

Details Semiconductor memory with selectively enabled precharge and sens Semiconductor memory with selectively enabled precharge and sens

1982-07-06

1985-07-09

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365230, 365227, G11C 1140

Patent

active

045286469

ABSTRACT:
Bit line precharge circuits, sense AMP circuits and input-output line precharge circuits are respectively divided into two groups by select circuits which are controlled by a select control signal. Only the selected precharge circuits and the sense AMP circuits are enabled before a readout operation. The peak current for precharging bit lines is reduced to one-half as compared to conventional circuits due to the decrease of stray capacitance to be precharged.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting
patent: 4112512 (1978-09-01), Arzubi et al.
patent: 4161040 (1979-07-01), Satoh
patent: 4204277 (1980-05-01), Kinoshita
patent: 4263664 (1981-04-01), Owen et al.
patent: 4281399 (1981-07-01), Yamamoto
patent: 4318014 (1982-03-01), McAlister et al.
patent: 4350992 (1982-09-01), Tubbs
patent: 4367538 (1983-01-01), Shimada
patent: 4379344 (1983-04-01), Ozawa et al.
patent: 4405996 (1983-09-01), Stewart

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