Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-08-09
1999-09-21
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438648, 438653, H01L 21441
Patent
active
059566124
ABSTRACT:
A contact space filled with conductive material having good step coverage is disclosed. The contact space is formed in a dielectric layer with an upper surface. The contact space has sidewalls comprised of the dielectric layer and a bottom comprised of an underlying layer. The contact space is filled by first depositing a layer of an amorphous material such as TiAl.sub.3 over the bottom and sidewalls of the contact space, then filling the contact space with a metallic fill material such as an aluminum-containing fill material. The amorphous material is chosen particularly to have low reactivity with the metallic fill material, so that mobility of the metallic fill material over the surface upon which it is deposited is facilitated.
REFERENCES:
patent: 3380657 (1968-04-01), Farrar
patent: 4310568 (1982-01-01), Howard et al.
patent: 4502209 (1985-03-01), Eizenberg et al.
patent: 4796082 (1989-01-01), Murakami et al.
patent: 4897709 (1990-01-01), Yokoyama et al.
patent: 5066611 (1991-11-01), Yu
patent: 5262354 (1993-11-01), Cote et al.
patent: 5312775 (1994-05-01), Fujii et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5358616 (1994-10-01), Ward
patent: 5401675 (1995-03-01), Lee et al.
patent: 5449421 (1995-09-01), Hamajima et al.
patent: 5543357 (1996-08-01), Yamada et al.
patent: 5610103 (1997-03-01), Xu et al.
patent: 5633200 (1997-05-01), Hu
patent: 5668054 (1997-09-01), Sun et al.
T. Iljima, et al. "Inlaid Cu Interconnects Employing Ti-Si-N Barrier Metal for ULSI Applications" IEICE Transactions on Electronics vol. E79-C No. 4. pp. 568-572. (abstract only), Apr. 1996.
Elliott Richard L.
Givens John H.
Hudson Guy F.
Everhart Caridad
Micro)n Technology, Inc.
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