Semiconductor memory circuit

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365203, G11C 700

Patent

active

044020660

ABSTRACT:
A semiconductor memory circuit having reduced read-access time and comprising a plurality of first and second common line pairs, each including a bit line and a data line connected in series is disclosed. Conventional static RAM memory cells are connected between each of the bit line pairs. A write-control circuit and sense amplifier are connected between each of the data bus pairs. At least one bypassing transistor is connected between each of the first and second common line pairs for conducting current between each of the lines of the common line pairs, thus reducing the read-access time.

REFERENCES:
patent: 4099265 (1978-07-01), Abe
patent: 4161040 (1979-07-01), Satoh

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