Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-02
1999-09-21
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438253, H01L 218242
Patent
active
059565861
ABSTRACT:
A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bit line and a capacitor are formed on the semiconductor layer. The semiconductor layer has a substantially flat upper surface, and an interlayer insulating layer and a second interlayer insulating layer having substantially flat upper surfaces are formed on the semiconductor layer. A capacitor is formed on the second interlayer insulating layer, and the capacitor and the second interlayer insulating layer are covered with a third interlayer insulating layer. Thereby, a level difference between a memory cell array and a peripheral circuitry can be reduced in a semiconductor memory device.
REFERENCES:
patent: 4561170 (1985-12-01), Doering
patent: 5218217 (1993-06-01), Oda et al.
patent: 5486712 (1996-01-01), Arima
patent: 5736421 (1998-04-01), Shimomura et al.
patent: 5753550 (1998-05-01), Murata et al.
patent: 5780351 (1998-07-01), Arita et al.
Chang Joni
Mitsubishi Denki & Kabushiki Kaisha
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