Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-02-17
1999-07-06
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438234, 438238, H01L 218238, H01L 218249
Patent
active
059207744
ABSTRACT:
A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated by using double diffused drain (DDD) ion implantation technology. In the functional region, MOSFETs structure are ion implanted by utilizing a large angle pocket antipunchthrough, succeeded using a lightly doped drain implantation technology with a liquid phase deposition (LPD) oxide layer in the ESD protective region as a mask. Next, a first thermal process is applied to form self-aligned silicide contacts. A low energy, high dose ion implantation implanted into silicide is then carried out, which is used as a diffusion source for forming an ultra-shallow junction. After that, a second rapid thermal process (RTP) is employed, an ultra-shallow junction, and low-resistivity stable phase of self-aligned silicide contacts in the functional region and a double diffusion junction in the ESD protective region are formed simultaneously.
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Lebendritt Michael S.
Niebling John F.
Texas Instruments - Acer Incorporate
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