Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1997-09-19
1999-07-06
Nelms, David
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365194, 365233, 36523008, G11C 1604
Patent
active
059205105
ABSTRACT:
A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.
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Akioka Takashi
Maejima Hideo
Mitsumoto Kinya
Nagano Takahiro
Yukutake Seigou
Hitachi , Ltd.
Nelms David
Nguyen Tuan T.
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