Static memory with pull-up circuit for pulling-up a potential on

Details Static memory with pull-up circuit for pulling-up a potential on Static memory with pull-up circuit for pulling-up a potential on

1987-12-22

1989-03-14

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365184, 307530, G11C 700, G11C 1134

Patent

active

048130222

ABSTRACT:
The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.

REFERENCES:
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patent: 4433393 (1984-02-01), Ontami
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patent: 4459497 (1984-07-01), Kuo et al.
patent: 4491741 (1985-01-01), Parker
patent: 4539494 (1985-09-01), Kurafuki
patent: 4636983 (1987-01-01), Young et al.
patent: 4658382 (1987-04-01), Tran et al.
patent: 4748349 (1988-05-01), McAlexander, III et al.
Minato et al., "A 20ns 64K CMOS SRAM," IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 222-223, Feb. 1984.

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