Method of manufacturing doped interconnect

Details Method of manufacturing doped interconnect Method of manufacturing doped interconnect

1996-11-05

1998-11-17

Graybill, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438625, 438647, 438649, H01L 2128

Patent

active

058376020

ABSTRACT:
A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed. For electrical interconnection of different types of diffusion regions with a polyside layer, the polysilicon layer is formed on only the innerside wall of the contact hole exposing the n.sup.+ and the p.sup.+ is diffusion regions and on the surface of the n.sup.+ and p.sup.+ diffusion regions, and the polyside layer is formed on the other regions, to thereby prevent the increase of the contact resistance.

REFERENCES:
patent: 4727045 (1988-02-01), Cheung et al.
patent: 4740479 (1988-04-01), Neppl et al.
patent: 5223456 (1993-06-01), Malwah
patent: 5237196 (1993-08-01), Mikata et al.
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patent: 5459101 (1995-10-01), Fujii et al.
"Dual (n+/p+) Polycide Interconnect Technology Using Poly-Si/WSi2/poly-Si Structure And Post B+ Implantation," by Toyokazu Fujii, Shin Hashimoto, Yasushi Naito and Yuichi Hirofuji.; IEDM 92-845, (1992).

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