Method of reducing stress-induced defects in silicon

Details Method of reducing stress-induced defects in silicon Method of reducing stress-induced defects in silicon

1995-09-12

1998-11-17

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438448, 438225, 438297, H01L 2176

Patent

active

058373780

ABSTRACT:
A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a portion of the masking stack on the bottom surface prior to forming isolation regions on the top surface of the semiconductor wafer. In one embodiment, silicon nitride is formed on the top and the bottom surface of a silicon wafer. The silicon nitride is then patterned and etched on the top surface of the wafer to expose regions of the underlying silicon for field oxide formation. Prior to the field oxidation formation on the top side of the wafer, the silicon nitride layer on the bottom side of the wafer is removed so that a layer of silicon dioxide is formed on the bottom surface of the wafer during field oxidation formation. The layer of silicon dioxide on the bottom surface of the wafer reduces the stress in the regions of the silicon wafer adjacent the top surface of the wafer and thereby reduces the formation of stress induced defects in this region of the silicon wafer. The layer of silicon dioxide on the bottom surface of the wafer can then be removed.

REFERENCES:
patent: 4125427 (1978-11-01), Chen et al.
patent: 5338968 (1994-08-01), Hodges et al.
Wolf, Stanley, "Basic Isolation Process for MOS ICs (Locos Isolation)", Silicon Processing for the VLSI Era vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, pp. 17-31, 1990.
Wolf, "Silicon Processing for The VLSI Era", vol. 2, Process Integration, Lattice Press, 1990, pp. 20-33.

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