NMOS input receiver circuit

Details NMOS input receiver circuit NMOS input receiver circuit

1998-11-11

1999-12-14

Phan, Trong

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365226, 36523008, G11C 1604, G11C 700, G11C 800

Patent

active

060026189

ABSTRACT:
An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.

REFERENCES:
patent: 4406957 (1983-09-01), Atherton
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4593212 (1986-06-01), Svager
patent: 4612461 (1986-09-01), Sood
patent: 4672243 (1987-06-01), Kirsch
patent: 4786830 (1988-11-01), Foss
patent: 4791323 (1988-12-01), Austin
patent: 4794283 (1988-12-01), Allen et al.
patent: 5079439 (1992-01-01), Wanlass
patent: 5144167 (1992-09-01), McClintock
patent: 5151620 (1992-09-01), Lin
patent: 5151622 (1992-09-01), Thrower et al.
patent: 5304867 (1994-04-01), Morris

Affiliated with

Also associated with

Rating

NMOS input receiver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with NMOS input receiver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NMOS input receiver circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-869635