Method of making a barrier layer to protect programmable antifus

Details Method of making a barrier layer to protect programmable antifus Method of making a barrier layer to protect programmable antifus

1997-07-30

1998-09-15

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438131, 438467, 257 50, 257530, H01L 2144

Patent

active

058077863

ABSTRACT:
A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via an insulator refill procedure, offers a smooth surface for the overlying antifuse layer.

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