Method of making a double stair-like capacitor for a high densit

Details Method of making a double stair-like capacitor for a high densit Method of making a double stair-like capacitor for a high densit

1997-11-03

1998-09-15

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 218242, H01L 2120

Patent

active

058077774

ABSTRACT:
A stacked layer is formed over a sunstrate. The stacked layer consists of at least three, preferably four, layers with different etching rates under a certain etchant with one another. An etching is used to etch the stacked layer to define a storage node using a photoresist as a mask. Then, a selectively etching is performed to etch the stacked layer. A polysilicon layer is than conformily formed along the surface of the stacked layer. Then, an anisotropically etching is carried out to etch the polysilicon layer. The polysilicon layer on the top of the stacked layer is completely removed to expose the top layer of the stacked layer. Next, the stacked layer is removed to form two stair-like structures. A dielectric layer is deposited along the surface of stair-like structures. Finally, a conductive layer is deposited over the dielectric layer.

REFERENCES:
patent: 5104821 (1992-04-01), Choi et al.
patent: 5637523 (1997-06-01), Fazan et al.
patent: 5656536 (1997-08-01), Wu
Watanabe, H. et al, "A New Cylindrical Capacitor using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs", IEDM, 1992, pp. 259-262.
Sakao, M. et al, "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs", IEDM, 1990, pp. 655-658.

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