Method of fabricating split-gate flash memory

Details Method of fabricating split-gate flash memory Method of fabricating split-gate flash memory

1998-03-23

1999-01-05

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438279, 438305, H01L 218247

Patent

active

058562249

ABSTRACT:
A method of fabricating split-gate slash memory can define source and drain regions by using a self-alignment process. Thus, the uniformity of the split-gate flash memory performance is better controlled. This method comprises a floating gate oxide layer, a first polysilicon layer and a mask layer formed sequentially over a first type substrate. The mask layer and the first polysilicon layer are patterned to form a floating gate. A photoresist layer is coated over the substrate and then a pattern is defined on the photoresist layer to expose portion of the substrate. Second type ions are implanted into the exposed substrate to form a drain region. Then, the photoresist layer is removed. An insulating layer is formed over the substrate and then is etched back to form spacers on one side of the floating gate. The second type ions are implanted into the substrate to form a source region. The spacers and the mask layer are removed. A control gate layer and a control gate are formed sequentially over the substrate.

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patent: 5633185 (1997-05-01), Yiu et al.
patent: 5674767 (1997-10-01), Lee et al.
patent: 5705416 (1998-01-01), Kim et al.

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