Method of fabricating a CMOS transistor

Details Method of fabricating a CMOS transistor Method of fabricating a CMOS transistor

1996-08-22

1999-01-05

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438225, 438297, 257274, H01L 218238

Patent

active

058562150

ABSTRACT:
The present invention relates to a method of fabricating a CMOS transistor which can further reduce the size of a chip since it is not necessary to consider the metal contact process margin since a gate electrode of a PMOS transistor and a gate electrode of an NMOS transistor are directly connected with a polysilicon wiring during a process of forming the gate electrodes, which can prevent the formation of a parasitic transistor by forming a cell space region in an active region below the polysilicon wiring.

REFERENCES:
patent: 4782037 (1988-11-01), Tomozawa et al.
patent: 4853340 (1989-08-01), Komatsu
patent: 5338986 (1994-08-01), Kurimoto
patent: 5464789 (1995-11-01), Saito
patent: 5506161 (1996-04-01), Orlowski et al.

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