Method of making titanium silicide source/drains and tungsten si

Details Method of making titanium silicide source/drains and tungsten si Method of making titanium silicide source/drains and tungsten si

1997-08-18

1999-08-03

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438655, H01L 21336

Patent

active

059337419

ABSTRACT:
A method for making low sheet resistance gate electrodes and low contact resistance source/drain areas on FETs has been achieved. The method involves patterning on a silicon substrate FET gate electrodes from polysilicon and a silicon-rich tungsten silicide (WSi.sub.x) layer, where x is about 2.5. FET Lightly Doped source/Drain (LDD) areas are formed adjacent to the gate electrodes. Then sidewall spacers are formed on the gate electrodes. The substrate is then thermally oxidized to form a cap oxide (SiO.sub.2) on the WSi.sub.x gate electrodes that is thicker than the silicon oxide grown concurrently on the source/drain areas. The thinner oxide is etched off the source/drain areas while a portion of the thicker cap oxide is retained on the gate electrodes. Titanium (Ti) is deposited and annealed to form TiSi.sub.2 source/drain areas, and the unreacted Ti is selectively removed on the cap oxide over the WSi.sub.2. Heavily doped source/drain junctions are formed by ion implanting through the TiSi.sub.2 to complete the FETs. This method provide FETs with gate electrodes having low sheet resistance and shallow diffused source/drain junctions with low contact resistance, thereby improving circuit performance. The invention also eliminates the silicide bridging problem associated with the conventional salicide process.

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