Method for manufacturing well structure in integrated circuit

Details Method for manufacturing well structure in integrated circuit Method for manufacturing well structure in integrated circuit

1998-01-21

1999-08-03

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438223, 438228, 438229, H01L 218238

Patent

active

059337222

ABSTRACT:
A method for forming a well structure in an integrated circuit such that, without any additional masking steps, the well implantation can be performed before the definition of the active device area. Hence, besides being able to avoid problems caused by a low breakdown voltage, also can provide a self-alignment mark for subsequent mask alignment, thereby reducing misalignment errors.

REFERENCES:
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patent: 4325169 (1982-04-01), Ponder et al.
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4435896 (1984-03-01), Parrillo et al.
patent: 4516316 (1985-05-01), Haskell
patent: 5627099 (1997-05-01), Sasaki
patent: 5744372 (1998-04-01), Bulucea
patent: 5795802 (1998-08-01), Ko et al.

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