Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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365189, G11C 700

Patent

active

047409266

ABSTRACT:
A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.

REFERENCES:
patent: 3949385 (1976-04-01), Sonoda
patent: 4112512 (1978-09-01), Arzubi et al.
patent: 4122548 (1978-10-01), Heuber et al.

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