Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-12-08
1999-12-07
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438259, 438275, H01L 21336
Patent
active
059982616
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION DESCRIPTION OF THE RELATED ART
Many applications require read-only memory cell arrangements with electrically writable and electrically erasable silicon-technology read-only memory cells, so-called EEPROMs. The stored data remain in these EEPROM arrangements even in the absence of a supply voltage.
From the technical point of view, these memory cells are usually produced by an MOS transistor which has, on the channel region, a first dielectric, a floating gate, a second dielectric and a control gate. If a charge is stored on the floating gate, then this charge affects the threshold voltage of the MOS transistor. In such a memory cell arrangement, the state "charge on the floating gate" is assigned to a first logic value, and the state "no charge on the floating gate" is assigned to a second logic value. The information is written into the memory cells by using a Fowler-Nordheim tunnelling current or by a "hot electron" current, by which electrons are injected onto the floating gate. The information is erased by a tunnelling current through the first dielectric. At least eight EEPROM transistors are connected to one another the other in series in a NAND arrangement.
The MOS transistors are designed as planar MOS transistors and are arranged in a planar cell architecture. The minimum area required for a memory cell is therefore equal to 4F.sup.2, F being the smallest producible structure size in the respective technology. EEPROM arrangements of this type are currently offered for maximum data volumes of 32 Mbit.
JP-A 3-1574 proposes an electrically writable and erasable read-only memory cell arrangement which comprises, as memory cells, MOS transistors which are vertical to a main surface of a semiconductor substrate and have a floating gate and a control gate. Essentially parallel strip-shaped trenches are provided in the substrate. The vertical MOS transistors are arranged on the flanks of the trenches. In this case, the memory cells are in each case arranged on opposite flanks of the trenches. Strip-shaped doped regions, which comprise the source and drain regions of the MOS transistors, extend in each case at the trench bottom and on the main surface between neighboring trenches. These strip-shaped doped regions are produced by masked implantation after the trenches have been formed. Because of the unavoidable alignment inaccuracy when masking steps are used, the packing density which can be achieved in this memory cell arrangement is limited.
US-A 5 049 956 discloses an electrically writable and erasable memory cell arrangement which comprises vertical MOS transistors, with floating gate and control gate, arranged in point-like trenches. A continuous doped layer, which acts as a common source region for all the MOS transistors, is provided at the bottom of the trenches. In order to increase the coupling capacitance, the floating gates protrude above the surface of the substrate.
Larger volumes of data can currently be stored in readable and erasable form only in dynamic memory cell arrangements (DRAM) or on magnetic data carriers. A DRAM continuously requires a supply voltage in order to retain the stored data. In contrast, magnetic data carriers are based on mechanical systems with rotating storage media.
The object of the invention is to provide a method for the production of a read-only memory cell arrangement which can be produced with a low area requirement per memory cell.
SUMMARY OF THE INVENTION
The electrically writable and erasable read-only memory cell arrangement produced by the method according to the invention is fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semi-conductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in between, a first dielectric, a floating gate, a second dielectric and a c
REFERENCES:
patent: 5049956 (1991-09-01), Yoshida
patent: 5180680 (1993-01-01), Yang
patent: 5414287 (1995-05-01), Hong
patent: 5460989 (1995-10-01), Wake
patent: 5554550 (1996-09-01), Yang
IBM Technical Disclosure Bulletin, vol. 35, No. 4B, Sep. 1992, "Vertical Eeprom Cell", pp. 130-131.
Hofmann Franz
Krautschneider Wolfgang
Risch Lothar
Rosner Wolfgang
Chang Joni
Siemens Aktiengesellschaft
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