Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-13
1999-12-07
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, H01L 218242
Patent
active
059982578
ABSTRACT:
In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate. The upper insulating layer is etched relative to the interposed conductive layer to form a capacitor container first portion. Subsequently, the interposed conductive layer is etched to form a capacitor container second portion.
REFERENCES:
patent: 5170233 (1992-12-01), Liu et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5227325 (1993-07-01), Gonzalez
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5244826 (1993-09-01), Gonzalez et al.
patent: 5323038 (1994-06-01), Gonzalez et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5401681 (1995-03-01), Dennison
patent: 5444013 (1995-08-01), Akram et al.
patent: 5581093 (1996-12-01), Sakamoto
patent: 5600177 (1997-02-01), Yamazaki
patent: 5610101 (1997-03-01), Koyama
patent: 5665626 (1997-09-01), Cronin
patent: 5677227 (1997-10-01), Yang et al.
patent: 5688713 (1997-11-01), Linliu et al.
patent: 5706164 (1998-01-01), Jeng
patent: 5717250 (1998-02-01), Schuele et al.
Lane Richard H.
Zahurak John K.
Micro)n Technology, Inc.
Tsai Jey
LandOfFree
Semiconductor processing methods of forming integrated circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor processing methods of forming integrated circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing methods of forming integrated circuitry will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-822997