Method for manufacturing an electrically writeable and erasable

Details Method for manufacturing an electrically writeable and erasable Method for manufacturing an electrically writeable and erasable

1997-11-11

1999-03-16

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438702, 257316, H01L 21336, H01L 2978

Patent

active

058829695

ABSTRACT:
In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.

REFERENCES:
patent: 5498560 (1996-03-01), Sharma et al.
patent: 5610419 (1997-03-01), Tanaka

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