Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Patent
1994-11-03
1996-12-03
Westin, Edward P.
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
326 47, 326113, 257206, H01L 2700
Patent
active
055812023
ABSTRACT:
The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.
REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 4745084 (1988-05-01), Rowson et al.
patent: 4870302 (1989-09-01), Freeman
patent: 5038192 (1991-08-01), Bonneau et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5132571 (1992-07-01), McCollum et al.
patent: 5378094 (1995-01-01), Suzuki et al.
Pasternak, John H., et al. "Differential Pass-Transistor Logic", IEEE Circuits and Devices, Jul. 1993, pp. 23-28. (English)
Yano, Kazuo et al. "A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic", IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 388-395. (English)
Kado, Y., et al. "Speed Performance of Pass Transistor Logic Gate Using CMOS/SIMOX Process", The Institute of Electronics Information and Communication Engineers of Japan, Spring Meeting, C-560, pp. 5-181, 1992. (Japanese)
Sasaki Yasuhiko
Yano Kazuo
Hitachi , Ltd.
Santamauro Jon
Westin Edward P.
LandOfFree
Semiconductor integrated circuit device and production method th does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and production method th, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and production method th will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-788423