Memory with selectively active input/output buffers

Details Memory with selectively active input/output buffers Memory with selectively active input/output buffers

1993-03-04

1994-11-29

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365195, G11C 700

Patent

active

053696115

ABSTRACT:
In a random access memory comprising pairs of input/output bus lines (7.sub.0 to 7.sub.3) transferring write data to the memory cells (3a) and read data from the memory cells, input/output terminals (10.sub.0 to 10.sub.3) corresponding to the pairs of input/output bus lines, and input/output buffer circuits (9.sub.0 to 9.sub.3) respectively corresponding to the input/output terminals and also corresponding to said input/output terminals, an access control signal is applied to the input/output terminal (10.sub.0) in a period in which the input/output terminal is not used for input or output of write data or read data, and transfer of read data through each of the input/output buffer circuits is permitted or inhibited on the basis of the access control signal.

REFERENCES:
patent: 4669064 (1987-05-01), Ishimoto
patent: 4742487 (1988-05-01), Bernstein
patent: 4760562 (1988-07-01), Ohtani
patent: 4982366 (1991-01-01), Takemae
patent: 5003510 (1991-03-01), Kamisaki
patent: 5073872 (1991-12-01), Masuda et al.

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