Integrated circuit and test method therefor

Details Integrated circuit and test method therefor Integrated circuit and test method therefor

1997-08-05

1999-10-26

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714734, G01R 3128

Patent

active

059745789

ABSTRACT:
In a mixed signal integrated circuit containing both an analog core circuit and a digital core circuit, a plurality of dedicated analog boundary scan cells disposed around the analog core circuit are connected in series by a dedicated analog boundary scan path. A plurality of dedicated digital boundary scan cells disposed around a digital core circuit are connected in series by a dedicated digital boundary scan path. The analog and digital boundary scan paths are independent of each other. In testing the analog or digital core circuit, the boundary scan path dedicated thereto is selected so that sets of test control data or test data are shifted only in the boundary scan cells dedicated thereto. As a consequence, a test pattern is shortened and the analog or digital core circuit can efficiently be tested in a shorter period of time.

REFERENCES:
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patent: 5416409 (1995-05-01), Hunter
patent: 5506851 (1996-04-01), Fuse
patent: 5793778 (1998-08-01), Qureshi
K.P. Parker, et al., "Structure and Metrology for an Analog Testability Bus", Proceeding of International Test Conference 1993, Paper 15.2, pp. 390-322, 1993.
An unapproved 1997 IEEE Standard Draft, subject to change, D15, p. 58 and 65, May 16, 1997.

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