Method of making MOS transistors with a gate-side air-gap struct

Details Method of making MOS transistors with a gate-side air-gap struct Method of making MOS transistors with a gate-side air-gap struct

1997-12-29

1999-10-26

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438595, 438657, H01L 21336

Patent

active

059727616

ABSTRACT:
This invention proposes a new process to form MOS transistor with a gate-side air-gap structure and an extension ultra-shallow S/D junction for high speed devices. After growing the thin gate oxide film on silicon substrate, a stacked-amorphous-Si (SAA) film is deposited. A thin CVD oxide film is deposited and then patterned. The top two amorphous-Si layers are etched back and then form the nitride spacers. The pad CVD oxide film is removed by diluted HF solution followed by S/D/G implant. High temperature thermal oxidation process is used to convert the bottom amorphous-Si layers outside the nitride spacers into thermal oxide and simultaneously to form shallow junction. The nitride spacers are removed and then the low energy/high dose ion implantation is performed for extension S/D junction. The bottom amorphous-Si layer is etched back and then RTP anneal in N.sub.2 O or NO ambient is used to recover the etching damage to form an extension S/D junction. A thick CVD oxide film is deposited on all regions. Due to the step coverage issue, a air-gap structure would be formed at the gate side.

REFERENCES:
patent: 5518960 (1996-05-01), Tsuchimoto
patent: 5585295 (1996-12-01), Wu
patent: 5641708 (1997-06-01), Sardella et al.
Shye Lin Wu et al., Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (.ltoreq.7nm) by Using a Stacked-Amorphous-Silicon (SAS) Film, 1993 IEEE, pp. 329-332.
Kyoji Yamashita et al., Impact of the Reduction of the Gate to Drain Capacitance on Low Voltage Operated CMOS Devices, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 69 and 70.
Atsushi Hori et al., High Speed 0.1 .mu.m Dual Gate CMOS with Low Energy Phosphorus/Boron Implantation and Cobalt Salicide, 1996 IEEE, pp. 575-578.
M. Togo et al., A Gate-Side Air-Gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSETs, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 38 and 39.
Bijan Davari, CMOS Technology Scaling 0.1.mu.m and Beyond, 1996 IEEE, pp. 555-558.

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