Electronic digital logic circuitry – Significant integrated structure – layout – or layout...
Patent
1994-01-26
1995-07-04
Hudspeth, David R.
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
327297, 327295, H03K 1900, H03K 500
Patent
active
054303974
ABSTRACT:
An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block. The intra-block clock distribution circuitry in each of the blocks responds to the block-destined clock signal supplied to the associated block via one of the block-based clock signal wires connected thereto and the intra-block clock signals fed back via the feedback wires in the associated block to thereby generate a plurality of intra-block clock signals having respective phases which depend on differences in phase between the block-destined clock signal and the fed-back intra-block clock signals.
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Itoh Hiroyuki
Maejima Hideo
Masuda Noboru
Nishimukai Tadahiko
Hitachi , Ltd.
Hudspeth David R.
Roseen Richard
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