Method of making semiconductor device having isolating trenches

Details Method of making semiconductor device having isolating trenches Method of making semiconductor device having isolating trenches

1995-06-06

1997-09-09

Nelms, David C.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

257315, 257316, 257397, 43818533, G11C 1134

Patent

active

056663110

ABSTRACT:
Disclosed is a semiconductor memory device which has memory cell transistors each comprising a liner source diffusion layer, a land-shaped drain diffusion layer, a gate oxide film containing a floating gate formed on the channel region between those diffusion layers, and a control gate formed on the gate oxide film. Trenches are formed in the substrate in no contact with the channel regions to isolate the cell transistors from each other.

REFERENCES:
patent: 4698900 (1987-10-01), Esquivel
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 5278438 (1994-01-01), Kim et al.
patent: 5445981 (1995-08-01), Lee
Hisamune et al., "A 3.b .mu.m.sup.2 Memory Cell Structure for 16 MB EPROMs", IEDM Technical Digest, Dec. 1989, pp. 583-586.

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