Method to increase surface area of a storage node electrode, of

Details Method to increase surface area of a storage node electrode, of Method to increase surface area of a storage node electrode, of

1996-11-06

1998-01-20

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438596, H01L 218242

Patent

active

057100756

ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of a flat, lower polysilicon shape, contacting an underlying transistor region, and of an upper polysilicon shape, comprised of polysilicon spacers, on the sides of the lower polysilicon shape, protruding above the top surface of the flat, lower polysilicon shape. The polysilicon spacers are formed via LPCVD and anisotropic RIE procedures, in addition to the use of a lift off procedure, used to remove unwanted polysilicon spacers from an underlying silicon oxide surface. This storage node configuration results in an significant increase of surface area, when compared to storage nodes fabricated without the incorporation of polysilicon spacers.

REFERENCES:
patent: 5137842 (1992-08-01), Chan et al.
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5447882 (1995-09-01), Kim
patent: 5491103 (1996-02-01), Ahn et al.

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