Semiconductor memory device with a fully accessible redundant me

Details Semiconductor memory device with a fully accessible redundant me Semiconductor memory device with a fully accessible redundant me

1997-11-25

1999-09-28

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

059599065

ABSTRACT:
A semiconductor memory device is shown that includes a normal memory cell array including a plurality of memory cells specified by 2.sup.n word lines and a plurality of column bit lines where an externally input n-bit row address is decoded to activate one of the 2.sup.n word lines. The semiconductor memory device further includes a redundant row fuse decoder that includes a plurality of n-bit address fuse portions each of which can be selectively coded to respond to an n-bit defective row address value in the externally input n-bit row address which corresponds to a word line in the normal memory cell array that includes a defective memory cell. The semiconductor memory device further includes a redundant memory cell array including a plurality of rows of memory cells which can be activated by one of the n-bit address fuse portions in response to the defective row address coded into the n-bit address fuse portion.

REFERENCES:
patent: 5386386 (1995-01-01), Ogihara
patent: 5708619 (1998-01-01), Gillingham
patent: 5768198 (1998-06-01), Moroo

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