Semiconductor memory

Details Semiconductor memory Semiconductor memory

1994-05-31

1995-04-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365233, G11C 1300

Patent

active

054084385

ABSTRACT:
Plural memory cells are connected to a common word line. Provided in each memory cell are a bit line pair, a data line pair, a precharge circuit, a switch circuit, a timing control circuit, and a sense amplifier. Each timing control circuit provides a word line control signal and a switch control signal, before the output of the sense amplifier becomes definite and at a point in time when the potential of the bit line pair changes to such an extent that the sense amplifier becomes operatable. The switch control signal is applied to a corresponding switch circuit to separate the sense amplifier from the bit line pair. The word line control signal From each timing control circuit is applied to a single OR gate. The output of the OR gate, along with the output of a row decoder, is applied to an AND gate. The AND gate controls the word line for activation. When every word line control signal becomes LOW, the word line is made inactive to separate all the memory cells from the corresponding bit line pairs.

REFERENCES:
patent: 3680061 (1972-07-01), Arbab et al.
patent: 3849673 (1974-11-01), Koo
patent: 4727517 (1988-02-01), Ueno et al.
patent: 4982365 (1991-01-01), Ohtani et al.

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