Method and apparatus for reducing latency time on an interface b

Details Method and apparatus for reducing latency time on an interface b Method and apparatus for reducing latency time on an interface b

1996-03-01

1998-09-29

Sheikh, Ayaz R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395285, 395286, 395878, 395880, 395847, 711167, H01J 1300

Patent

active

058156739

ABSTRACT:
Customized circuitry implemented on the transmitting end of an interchip communication bus reduces the number of clock cycles required to transmit control packets over the interchip communication bus. The packet transaction protocol is predicated upon the relationship between consecutive command words sent over the interchip bus so that, if consecutive words at a packet boundary contain the same data, this data can be saved as separate command words by the receiving chip within a single clock cycle. This is accomplished through the generation of a synchronization signal whenever a new packet is started. In a preferred embodiment, bit patterns for the first and/or last word of a packet which are found to be statistically more prevalent are intentionally juxtaposed to increase the probability of consecutive command words having the same information.

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