Method of fabricating totally self-aligned contacts for dynamic

Details Method of fabricating totally self-aligned contacts for dynamic Method of fabricating totally self-aligned contacts for dynamic

1995-12-27

1997-09-09

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

148DIG20, 438297, 438453, 438666, H01L 218242

Patent

active

056656238

ABSTRACT:
A method is provided for fabricating totally self-aligned contacts on semiconductor substrates. The method is particularly applicable to dynamic random access memory for reducing the cell area. The method involves patterning the silicon nitride layer for the local oxidation of silicon (LOCOS) process to provide wide device areas for the gate electrode of the FETs, and narrow device areas adjacent and contiguous to the wide device areas on and in which are formed portions of the source/drain areas and the totally self-aligned contacts. The lateral encroachment of the field oxide (bird's beak) into the narrow device areas during the LOCOS process reduce the width of the area to about 0.20 um, and thereby extend the resolution limit of the current lithography (about 0.40 um) used to define the nitride layer. Non-critically aligned contact openings etched in an insulating over the narrow device areas, and extending over the field oxide region (bird's beak) and over the insulated gate electrodes result in totally self-aligned contacts defined by the bird's beak structures and gate electrodes.

REFERENCES:
patent: 5275974 (1994-01-01), Ellul et al.
patent: 5376577 (1994-12-01), Roberts et al.
patent: 5393704 (1995-02-01), Huang et al.
patent: 5521113 (1996-05-01), Hsue et al.
"Processes of the Future" Solid State Technology, pp. 42-54, Feb. 1995.

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