Power reduction circuits and systems for dynamic logic gates

Details Power reduction circuits and systems for dynamic logic gates Power reduction circuits and systems for dynamic logic gates

1996-07-19

1998-09-29

Nelms, David C.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 93, H03K 19096

Patent

active

058150056

ABSTRACT:
In a preferred embodiment there is a logic circuit (230) which includes both a first (231) and second (232) phase dynamic logic circuit, where each such circuit has a one or more dynamic logic stages. Each dynamic logic stage includes a precharge node(231.sub.1PN), a coupling device (231.sub.1PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, a discharge path (231.sub.1DT) connected to the precharge node which when conducting couples the precharge node to a voltage (ground) different than the precharge voltage during an evaluate phase, and an output for presenting a logic value responsive to a voltage at the precharge node. The logic circuit further includes control circuitry (PHASE 1 and 2 CLOCKS and 234) for controlling at least one (231.sub.4) of the dynamic logic stages as a storing stage, such that the coupling device (231.sub.4PT) and the discharge path (231.sub.4DT) of the storing stage are concurrently not conducting during a predetermined time such that the logic value is maintained at the output. Specifically, the predetermined time is equal to or greater than a time period equal to the evaluate phase plus the precharge phase.

REFERENCES:
patent: 4710650 (1987-12-01), Shoji
patent: 4797580 (1989-01-01), Sunter
patent: 5532625 (1996-07-01), Rajivan

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