Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

1999-03-25

2000-02-29

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 365218, G11C 700

Patent

active

060317620

ABSTRACT:
There is provided a non-volatile semiconductor memory which is capable of establishing a proper reading voltage for an erasure threshold voltage and a proper writing time for the reading voltage by detecting the threshold voltages for writing and erasing in a memory cell array. The present non-volatile semiconductor memory, which is called a flash EEPROM, includes a first memory cell array 1, a second memory cell array 2, a row decoder 3, a line decoder 4, a reading control circuit 5, a writing and erasing control circuit 6, a writing time control circuit 7, a high voltage generating circuit 8, a counter circuit 13, a 1/N circuit 9, and a reading voltage generating circuit 11. The first memory cell array 1 and the second memory cell array 2 are formed on a same memory cell array, and all of the data stored in both memory cell arrays can be erased at once. Thus, all the memory cells in the memory cell array have the same erasure threshold voltage. The first memory cell array 1 is designated to be an area in which data can be freely written, and the second memory cell array 2 is designated as an area for detecting the threshold voltages of the memory cells so that it is not permitted to write in the second memory cell array 2 except when detecting the threshold voltage.

REFERENCES:
patent: 5687345 (1997-11-01), Matsubara et al.
patent: 5708605 (1998-01-01), Sato
patent: 5796652 (1998-08-01), Takeshima et al.
patent: 5828604 (1998-10-01), Kawai et al.
patent: 5835415 (1998-11-01), Marari

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