Method of manufacturing hemispherical grained polysilicon with i

Details Method of manufacturing hemispherical grained polysilicon with i Method of manufacturing hemispherical grained polysilicon with i

1998-03-25

1999-04-27

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218242

Patent

active

058973524

ABSTRACT:
A method for creating a stacked capacitor structure, with increased surface area, needed for high density, DRAM designs, has been developed. A storage node electrode, featuring a top surface of HSG polysilicon lumps, is used for the surface area increase. A feature of this invention is the use of a thin, heavily doped, polysilicon layer, formed on the HSG polysilicon lumps, resulting in improved adhesion between HSG polysilicon lumps and the underlying polysilicon storage node shape. The thin, heavily doped, polysilicon layer also supplies dopant to underlying HSG polysilicon lumps, needed to reduce a capacitor depletion phenomena which can occur if undoped HSG polysilicon lumps are used.

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