Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365154, G11C 700

Patent

active

048212377

ABSTRACT:
This invention provides a semiconductor memory device for reading and writing data comprising a pair of row lines, each having a corresponding electrical potential, the difference between the two potentials increasing during reading of data at least one static memory cell connected between the pair of row lines for storing data written into the memory cell and voltage control means for limiting the increase in the potential difference between the row lines during reading of the data from the memory cell to a predetermined amount for getting fast access time of the reading operation.

REFERENCES:
patent: 3849675 (1974-11-01), Waaben
patent: 4393471 (1983-07-01), Hart et al.
patent: 4578778 (1986-03-01), Aoyama
IBM Technical Disclosure Bulletin-vol. 27, No. 4A, Sep. 1984, pp. 1858-1859.
Isobe et al., "A 46ns 256K CMOS RAM", IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 214-215, Feb. 23, 1984.

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