Semiconductor memory device having plurality of equalizer contro

Details Semiconductor memory device having plurality of equalizer contro Semiconductor memory device having plurality of equalizer contro

1998-04-24

2000-08-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Precharge

36523006, G11C 700

Patent

active

060976489

ABSTRACT:
An equalizer control line BLEQ shared by all sense amplifiers SA in each row in each submat SM is connected to a first equalizer control line driver consisting of P-type MOS transistors installed at the left end of the submat SM and is connected to several second equalizer control line drivers 32 consisting of N-type MOS transistors installed by dividing in a cross area 16 of each row through which the equalizer control line BLEQ passes. In order to turn on the equalizers of the bit line pair connected to each sense amplifier S, the first equalizer control line driver is operated to drive the equalizer control line BLEQ to the H level potential. In order to turn off the equalizers of each bit line pair, the second equalizer control line drivers 32 are operated to drive the equalizer control line BLEQ to the L level potential. The first and second equalizer control line drivers are complementarily operated. One of them is driven, and the other is turned off (blocked).

REFERENCES:
patent: 5068831 (1991-11-01), Hoshi et al.
patent: 5623446 (1997-04-01), Hisada et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device having plurality of equalizer contro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having plurality of equalizer contro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having plurality of equalizer contro will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-670279