ESD protection clamp for mixed voltage I/O stages using NMOS tra

Details ESD protection clamp for mixed voltage I/O stages using NMOS tra ESD protection clamp for mixed voltage I/O stages using NMOS tra

1998-05-04

2000-08-01

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257500, 257 56, 257111, 257 91, 257118, 257117, 257119, 257126, 257127, 257346, 341137, 341155, H01L 2900, H01L 3120, H01L 2904

Patent

active

060970715

ABSTRACT:
An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region. This shared diffusion region is also the common node electrically coupling the first transistor's source to the second transistor's drain region, and is a further benefit of the invention because its length controls the trigger voltage and holding voltage of the cascode transistor pair. This electrostatic discharge protection device can be used either as a self protection pull-down portion of a mixed voltage I/O stage, or in a further aspect of the present invention, as a separate electrostatic discharge clamp.

REFERENCES:
patent: 5698873 (1997-12-01), Colwell et al.
patent: 5764464 (1998-06-01), Botker et al.
patent: 5850195 (1998-12-01), Berlien, Jr. et al.
Voldman, Steven H., "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50-and 0.25-um Channel Length CMOS Tehcnologies," Essex Junction, VT: IBM Microelectronics Division (1994).
Voldman, Steven H., "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50-and 0.25-.mu.m Channel Length CMOS Technologies," Essex Junction, VT: IBM Microelectronics Division (1994).

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