Method and configuration for reducing electrical noise in integr

Details Method and configuration for reducing electrical noise in integr Method and configuration for reducing electrical noise in integr

1993-06-30

1994-08-02

Picard, Leo P.

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

174251, 361813, 29841, 257787, 257792, H01L 2328

Patent

active

053348028

ABSTRACT:
A chip packaging configuration prevents differential electrical coupling within a plurality of associated bit lines (14 and 16) by associating, under lead frame (26), a first packaging material having a first dielectric constant and a second packaging material having a second dielectric constant and where the first packaging material and second packaging material are configured to expose the plurality of associated bit lines (14 and 16) to allow approximately equal coupling to lead frame (26) for each bit line (14 and 16) through the first and second dielectric constant to thereby prevent differential electrical coupling of the plurality of bit lines (14 and 16) with lead frame (26).

REFERENCES:
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4916519 (1990-04-01), Ward
patent: 4965654 (1990-10-01), Karner et al.
patent: 5153689 (1992-10-01), Okumura et al.
patent: 5197184 (1993-03-01), Crumly et al.
William C. Ward, IBM General Technology Division, Essex Junction, Vermont; "Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques"; IEEE, 0569-5503/88/0000-0552; pp. 552-557.

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