Method of forming self-aligned silicide in integrated circuit wi

Details Method of forming self-aligned silicide in integrated circuit wi Method of forming self-aligned silicide in integrated circuit wi

1998-08-17

2000-08-01

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438299, 438301, 438303, 438305, 438307, H01L 21336

Patent

active

060966424

ABSTRACT:
A method is provided for forming self-aligned silicide in integrated circuit, which can help prevent the occurrence of a bridging effect in the integrated circuit. This method is characterized in the provision of an elevated spacer structure that can act like a barrier to prevent the occurrence of a bridging effect between the polysilicon gate and the source/drain regions caused by the forming of undesired silicide over the spacer structure due to lateral diffusion of the silicide from the polysilicon gate. Moreover, this method is characterized in the use of two different materials to respectively form the sacrificial layer and the field oxide layers, thus allowing the field oxide layers to remain substantially intact during the removal of the sacrificial layer through etching. This feature can help prevent the occurrence of leakage current from the metal plug to the substrate.

REFERENCES:
patent: 5496750 (1996-03-01), Moslehi
patent: 5656519 (1997-08-01), Mogami
patent: 5686331 (1997-11-01), Song
patent: 5872039 (1999-02-01), Imai
patent: 5879997 (1999-03-01), Lee et al.
patent: 5891784 (1999-04-01), Cheung et al.
patent: 5902125 (1999-05-01), Wu

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