Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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365202, G11C 700

Patent

active

056527276

ABSTRACT:
A semiconductor memory device includes first and second MOS transistors connecting a pair of data lines with a specific potential supplying node. A power transmitting circuit couples the specific potential supplying node with a power supply circuit of an equalizing potential after said first and second switching elements are made conductive. The power transmitting circuit isolates the specific potential supplying node from the power supply circuit when the equalization begins. As an alternative to the power transmitting circuit, a supplying circuit may be connected to supply a precharge potential to the specific potential supplying node when the equalization begins, and supply an equalizing potential to the specific potential supplying node when the switching elements are both turned on.

REFERENCES:
patent: 4903238 (1990-02-01), Miyatake
patent: 5036492 (1991-07-01), Runaldue
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5247482 (1993-09-01), Kim
patent: 5325335 (1994-06-01), Ang et al.
patent: 5402378 (1995-03-01), Min et al.
patent: 5477496 (1995-12-01), Tanaka et al.

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