Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1985-08-02
1988-08-16
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365203, 365222, 365233, G11C 700, G11C 800
Patent
active
047649011
ABSTRACT:
The semiconductor memory device contains a plurality of memory cells, a row decoder for selectively actuating memory cells according to the selected one of the row and column address signals, and bit lines set to a potential dependent on the data in the memory cell actuated. Particularly, this memory device has latching circuits for latching the potentials on the bit lines, and a timing controller for causing the latching circuits to keep the latched potentials for a predetermined period after the update of the row address signal.
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O. Minato et al., "A 20 ns 64K CMOS SRAM," IEEE International Solid State Circuits Conference, pp. 222-223 and 343, vol. 27, 2-23-84.
J. J. Fallin, "The Chip That Refreshes Itself," Computer Design, pp. 111-122, vol. 22, No. 3, (Mar. 1983).
Kawamoto et al., "A 288Kb CMOS Pseudo SRAM," IEEE International Solid-State Circuits Conference, pp. 276-277, Feb. 24, 1984.
Garcia Alfonso
Hecker Stuart N.
Kabushiki Kaisha Toshiba
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