Static information storage and retrieval – Read/write circuit – Precharge
Patent
1994-02-25
1995-10-17
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Precharge
365 94, 365104, 36518901, G11C 1700
Patent
active
054596920
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The invention relates to a semiconductor memory device and, more particularly, to a Read Only Memory (hereinafter, called as ROM) and a method for reading the data therefrom.
BACKGROUND ART
A well known ROM in general is shown in FIG. 2. Referring to FIG. 2, a circuit structure of the ROM will be described hereinbelow. In order to simplify the description, some of N-channel MOS transistors (hereinafter, NMOS) are represented by a simplified sketch as shown in FIG. 3, and some of P-channel MOS transistors (hereinafter, PMOS) are also represented by a simplified sketch as shown in FIG. 4.
The ROM shown in FIG. 2 is constituted of a memory cell block MC for storing data, a Y-decoder YD for selecting (activating) word-lines Y1 to Y8, and an X-decoder XD for selecting bit-lines X1 to X16 (reference numerals of word-lines Y4 to Y7 and bit-lines X4 to X15 are not shown in FIG. 2). The Y-decoder YD is connected to a word-line discharge circuit WD in which a voltage of V.sub.SS level as a ground potential is supplied to the word-lines Y1 to Y8. And the word-lines Y1 to Y8 are connected to a word-line precharge circuit WP in which a voltage of V.sub.DD level as a power supply potential is supplied thereto (reference numerals of decode-lines AY4 to AY7 are not shown in FIG. 2).
On the other hand, decode-lines AX1 to AX16 in the X-decoder XD are commonly connected to a data terminal 225 (reference numerals of decode-lines AX4 to AX15 are not shown in FIG. 2). Then, the data terminal 225 is connected to a bit-line precharge circuit BP, in which the voltage of V.sub.DD level is supplied to the bit-lines X1 to X16, and further, to a data output terminal 221 through a data output buffer OB. Further, the bit-lines X1 to X16 are connected to a data output enable circuit DOE in which the voltage of V.sub.SS level is supplied thereto.
Next, each circuit structure in the ROM will be described in detail.
The memory cell block MC has a capacity of 128 bits and memory locations defined at cross-over positions at which respective word-lines and bit-lines intersect with each other. Then, NMOSs for storing data are arranged on the respective memory locations. For example, NMOSs h1 and h2 are connected in series to the bit-line X1 so that a gate of the NMOS h1 is connected to the word-line Y3 and a gate of the NMOS h2 is connected to the word-line Y7. That is, the NMOS h1 is arranged on the memory location (X1, Y3) defined by the word-line Y3 and the bit-line X1, likewise, the NMOS h2 is arranged on the memory location (X1, Y7) defined by the word-line Y7 and the bit-line X1. Further, any other NMOSs for storing data are not substantially arranged on the other memory locations of the bit-line X1.
Although all of the memory locations of the bit-line X1 practically have NMOSs respectively, no NMOS apparently appear except the NMOSs h1 and h2 by forming short-circuit between the sources and the drains with aluminum wire or the like, otherwise, by forming quasi short-circuit by using a method of ion implantation.
The Y-decoder YD is constituted of Y address terminals 209, 211, 213 to which Y address signals are provided, inverters e1 to e6 for inverting the Y address signals, and Y decode-lines AY1 to AY8 respectively connected to the word-lines Y1 to Y8. Each of the decode-lines is constituted of three NMOSs connected in series to one another, therefore, the Y-decoder YD is constituted of 24 NMOSs in total. These NMOSs are turned on in response to the Y address signals provided to Y address terminals 209, 211, 213.
On this moment, there exists only one Y decode-line on which all the three NMOSs connected in series are turned on. It is selected, a word-line connected to the selected Y decode-line.
The word-line discharge circuit WD is constituted of a precharge signal input terminal 229 to which a precharge signal P1 is provided, an inverter e7, NMOSs g41 to g48, and a V.sub.SS terminal 231 to which the voltage of V.sub.SS level is supplied (reference numerals of NMOSs g44 to g47 are not shown in FIG. 2). Each source
REFERENCES:
patent: 4240151 (1980-12-01), Kawagoe
patent: 4858194 (1989-08-01), Terada
Kodama Hidetaka
Shin Yasuhiro
Mai Son
Manzo Edward D.
OKI Electric Industry Co., Ltd.
Popek Joseph A.
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