Circuit and method for gate-body structures in CMOS technology

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257369, 257374, H01L 2701, H01L 2712, H01L 310392

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active

061076635

ABSTRACT:
A circuit and method for an improved inverter is provided. The present invention capitalizes on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (V.sub.t). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. This design provides fast switching capability for low power battery operated CMOS circuits and systems. The transistor structure offers performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

REFERENCES:
patent: 4450048 (1984-05-01), Gaulier
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4922315 (1990-05-01), Vu
patent: 4987089 (1991-01-01), Roberts
patent: 4996574 (1991-02-01), Shirasaki
patent: 5006909 (1991-04-01), Kosa
patent: 5097381 (1992-03-01), Vo et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5250450 (1993-10-01), Lee et al.
patent: 5315143 (1994-05-01), Tsuji
patent: 5350934 (1994-09-01), Matsuda
patent: 5379255 (1995-01-01), Shah
patent: 5491356 (1996-02-01), Dennison et al.
patent: 5508544 (1996-04-01), Shah
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5541432 (1996-07-01), Tsuji
patent: 5581104 (1996-12-01), Lowrey et al.
patent: 5585998 (1996-12-01), Kotecki et al.
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5680345 (1997-10-01), Hsu et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5796143 (1998-08-01), Fulford, Jr. et al.
patent: 5796166 (1998-08-01), Agnello et al.
patent: 5892260 (1999-04-01), Okumura
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-Mosfet's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).
Holman, W.T., et al., "A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology", IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).
Horiguchi, et al., "Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSIs", IEEE Journal of Solid State Circuits, vol. 28, 1131-1135, (1993).
Huang, W. L., et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).
Jaeger, et al., "A High-speed Sensing Scheme for 1T Dynamic RAMs Utilizing the Clamped Bit-line Sense Amplifier", IEEE Journal of Solid State Circuits, vol. 27, 618-25, (1992).
MacSweeney, D., et al., "Modelling of Lateral Bipolar Devices in a CMOS Process", IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, 27-30, (Sep. 1996).
Parke, S.A., et al., "A High-Performance Lateral Bipolar Transistor Fabricated on Simox", IEEE Electron Device Letters, 14, 33-35, (Jan. 1993).
Rabaey, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, NJ, 222-232, (1996).
Saito, M., et al., "Technique for Controlling Effective Vth in Multi-Gbit DRAM Sense Amplifier", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, 106-107, (Jun. 13-15, 1996).
Seevinck, E., et al., "Current-Mode Techniques for High-Speed VLSI Circuits with Applications to Current Sense Amplifier for CMOS SRAM's", IEEE Journal of Solid-State Circuits, 26, 525-536, (Apr. 1991).
Tsui, P.G., et al., "A Versatile Half-Micron Complementary BiCMOS Technology for Microprocessor-Based Smart Power Applications", IEEE Transactions on Electron Devices, 42, 564-570, (Mar. 1995).
Wong, et al., "A 1V CMOS Digital Circuits with Double-Gate Driven Mosfet", IEEE Int. Solid State Circuits Conference, San Francisco, 292-93, (1997).
Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Cicuits", IEEE Transactions of Electron Devices, 43, 904-909, (Jun. 1986).
Chen, M.J., et al., "Optimizing the Match in Weakly Inverted Mosfet's by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chung, I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30-Oct. 3, 1996).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).
Ko, et al., "High-gain Lateral Bipolar Action in a Mosfet Structure", IEEE Trans. on Electron Devices, vol. 38, No. 11, 2487-96, (Nov. 1991).
Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 68-69, (Feb. 6, 1997).
Tuinega, A Guide to Circuit Simulation and Analysis Using PSPICE, Prentice Hall, Englewood Cliffs, NJ, (1988).
Wolf, S., In: Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, CA, 389-392, (1990).

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