Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-12-30
2000-01-18
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, 714 28, 714 40, 39550044, 324754, G01R 3128, G06F 1100
Patent
active
060165634
ABSTRACT:
An apparatus and method are provided for the development, testing and verification of a logic design of a programmable logic device in a real-time user environment to simplify the development of the programmable logic device and associated systems. The apparatus comprises an emulation programmable logic device based on the same family and package of the target programmable logic device. The adapter further comprises a plurality of individually programmable switches for selectively coupling the emulation device to the target device or to a logic device substituting for the target device. The apparatus further comprises a controller, which configures the switches based on control signals received from a host computer system, such that a stimulus applied to the input pins of the target or substitute device are also applied concurrently to the corresponding input pins of the emulation device. The switches are further configured so that the output pins of the emulation device are unloaded from all of their normal functions and are output only as test points. Signal values at internal nodes of the emulation device in response to the stimulus can be traced out via the test points without disturbing the target or substitute device. The apparatus permits dynamic and independent programming and reprogramming of both the target and mirror devices, such that different internal nodes can be traced out quickly and easily. The apparatus may further include an embedded programmable stimulus generator and an embedded logic analyzer.
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Beausoliel, Jr. Robert W.
Shaw Brian H.
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