CMOS 3.3 volt output buffer with 5 volt protection

Details CMOS 3.3 volt output buffer with 5 volt protection CMOS 3.3 volt output buffer with 5 volt protection

1995-08-09

1996-11-12

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 83, 326 33, H03K 190948

Patent

active

055743897

ABSTRACT:
As VLSI chip design migrates from 5 volt designs to lower voltage designs, such as 3.3 volts, interfacing components with different power supplies is an unavoidable issue. This invention provides simple and inexpensive circuits which will pass the voltage at the output node of a CMOS buffer circuit to the isolation well of the P channel metal oxide semiconductor field effect transistor in the buffer circuit when the voltage at the output node is greater than the voltage at the buffer voltage supply node. This prevents forward biasing the PN junction in the isolation well of the P channel metal oxide semiconductor field effect transistor. The circuits also provide the proper voltage level to the gate of the P channel field effect transistor.

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