Registered outputs for a memory device

Details Registered outputs for a memory device Registered outputs for a memory device

1988-05-24

1990-03-13

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, 307475, G11C 700

Patent

active

049087967

ABSTRACT:
Registered output circuitry for a memory device includes a first latch which stores data from a sense amplifier on the rising edge, and outputs it on the falling edge, of the falling edge of an OE signal. This data stored in the latch is provided as output of only y, during the preceding rising edge of the OE signal the CE signal to the memory device was a logical 0 level, and the WE signal was a logical 1 level. Since the falling edge of the OE signal is the beginning of the memory cycle, the data at the output pin of the memory is the data read in the previous read cycle. This latency, however, enables a shortened average cycle time, and also provides registered outputs without the necessity of an external clock signal applied to the memory device.

REFERENCES:
patent: 4573147 (1986-02-01), Aoyama et al.
patent: 4575824 (1986-03-01), Tanaka et al.
patent: 4603403 (1986-07-01), Toda
patent: 4680491 (1987-07-01), Yokouchi et al.
patent: 4682048 (1987-07-01), Ishimoto
patent: 4703457 (1987-10-01), Bodenstab

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